1. Field of the Invention
The present invention relates to semiconductor manufacturing. More specifically, the present invention relates to a method and apparatus for modifying a layout to improve manufacturing robustness.
2. Related Art
The dramatic improvements in semiconductor integration densities in recent years have largely been made possible by corresponding improvements in semiconductor manufacturing technologies.
One such semiconductor manufacturing technology involves placing assist features in a mask layout. Assist features (AFs) can be printing (e.g., super-resolution assist features) or non-printing (e.g., sub-resolution assist features). In either case, assist features are meant to improve the depth of focus of the patterns intended to be printed on the wafer, while maintaining pattern fidelity.
Prior art techniques for placing assist features typically use mask rules, which place and cleanup assist features based on combinations of feature width and spacing parameters. Such rule-based approaches can result in missed or sub-optimal placement and/or cleanup of assist features. Further, the complexity of such rules increases rapidly with shrinking features size, thereby requiring more wafer data for calibration and more effort on the part of engineers. Moreover, these rules can be overly restrictive which can prevent designers from being able to achieve the best semiconductor device performance.
Another technique for improving manufacturing robustness involves resizing a line (changing the width of the line). However, as was the case with assist features, prior art techniques resize lines based on rule tables, which can result in missed or sub-optimal resizing.
Hence, what is needed is a method and apparatus for modifying a layout to improve manufacturing robustness without the above-described problems.